![]() Select the top-level design file to simulate. In the Name list, click the + icon to expand the work directory. In the Search Libraries (-L) box, click Add and select the appropriate libraries. If you are simulating a Verilog HDL design, to specify the ModelSim-Altera precompiled libraries: Repeat steps 2b to 2d to compile the testbench file(s). vo) for use in a functional simulation, you should compile it before proceeding. If you have generated a VHDL Output File (. ![]() Note: In the More EDA Netlist Writer Settings dialog box you can specify settings for generating functional simulation netlist files. In the Files of Type list, select All Files (*.*), and in the Look in list select the. In the File name list, type the directory path and file name of the. In the Library list of the Compile Source Files dialog box, select the work library. To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench): If you have not already done so, set up a project with the ModelSim-Altera software.
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